Example 1

The following snapshots are from models and simulations of a 108-processor Mercury Raceway system executing a signal processing algorithm. The snapshots show: The diagram on the left is the top-level software DFG for a hierarchical application.

(Click to see detail.)

Software application data-flow-graph.

The diagram on the right is the sub-graph which under-lies the super-node clutter from the top-graph. It is at the second level of the hierarchy. It was opened by double-clicking on the super-node from the top-level graph. The DFG's are converted into pseudo-programs by the SCHEDULER tool which maps and schedules the tasks to the processor elements.

The following snapshots show the hardware architecture of the modeled system. The snapshots are from simulation animations of the 108-processor Mercury Raceway system executing the application algorithm defined above. The colors indicate computations on processor elements and data transfers on network links.

(Click to enlarge or play animation.)

Modeled system hardware architecture during simulation.
(Diagram is zoomed-out to show full hardware architecture.)

When a link is requested for transferring data, it is colored yellow to indicate that a transfer is tentative. When data is flowing through a link, it is colored green. When there is a contention for a link, it is colored red. The snapshots below show instances of transfers and contentions.


Close-ups of portions of the system during simulation.

The following are the processing time-line graphs that resulted from the simulation.

(Click to see detail.)

Resulting processing time-lines.

The time-line on the left is a basic time-line with annotations identifying the operations. The time-line on the right over-lays communication events between processors for greater insight into the system's operation. We call the latter graph, a spider-web plot due to its appearance.