The above snapshot depicts the animation of instantaneous transfers and operations for the mapped application flow-graph onto the nine-board system. The processor nodes are colored to indicate when they are performing specific tasks. The C40 data-links are colored to indicate when data is flowing through them. The snapshot features CSIM's ability to display a hierarchical block-diagram as a flattened graph during simulation. The architecture contained two levels of hierarchy. Note that because this is a flattened diagram, sub-diagrams were expanded in-place, so the I/O vias on the boundary of the sub-diagrams do not necessarily align with their connections on the outer diagram.
The following are the processing time-line graphs that resulted from the simulation. The processing time-lines show when specific processor elements are performing tasks identified by the annotations.
The time-line on the left is a basic time-line with annotations identifying the operations. The time-line on the right over-lays communication events between processors for greater insight into the system's operation. We call the latter graph, a spider-web plot due to its appearance.