74xx-Series Models

A partial library of the standar 74xx-Series small scale integration (SSI) parts has been assembled. Although the original 74xx-series parts may not be used often, they are still useful for glue logic, and reflexions of the basic cell patterns reoccur throughout FPGA and custom cell families. This library was assembled originally to support conceptual testing and validation against widely available, measurable, and known parts. However, they are provided for convenience, completeness, and learning. Learning about a new modeling environment is often eased by familiar subject matter.

This library resolves the 74xx-series parts to the logic gate level. The logic gates possess inertial and propagation delay attributes, which can be set globally, per chip, and/or per gate.

The available models and their diagrams are listed below:

  1. demux2.sim - 1-to-4
    testbench - test_demux2.sim (demux.dat)

  2. jkFFwClrPre.sim - J-K Flip-Flop with Preset & Clear
    testbench - Test_jkFFwClrPre.sim (test_jkffWclrPre.dat)

  3. mux4.sim - 4 to 1 mux
    no testbench

  4. 74164.sim - 8-Bit Parallel-out Serial Shift Registers
    testbench - test_74164.sim (test_74164.dat)

  5. 74166.sim Parallel-Load 8-Bit Shift Registers
    testbench - test_74166.sim (test_74166.dat)

  6. 74181.sim - (partial, not completed)

  7. 74LS51.sim - AND-OR-Invert Gates
    no testbench

  8. 74LS54.sim - 4-Wide AND-OR-Invert Gates
    no testbench

  9. 74x00.sim - Quadruple 2-Input Positive-NAND Gates
    no testbench

  10. 74x01.sim - Quadruple 2-Input Positive-NAND Gates (open-collector outputs not modeled) no testbench

  11. 74x02.sim - Quadruple 2-Input Positive-NOR Gates
    no testbench

  12. 74x03.sim - Quadruple 2-Input Positive-NAND Gates (open-collector outputs not modeled) no testbench

  13. 74x04.sim - Hex INVERTERS
    no testbench

  14. 74x05.sim - Hex INVERTERS (open-collector outputs not modeled) no testbench

  15. 74x06.sim - Hex INVERTER BUFFERS (open-collector outputs not modeled) no testbench

  16. 74x07.sim - Hex BUFFERS/DRIVERS (open-collector outputs not modeled) no testbench

  17. 74x08.sim - Quadruple 2-Input Positive-AND Gates
    no testbench

  18. 74x09.sim - Quadruple 2-Input Positive-AND Gates (open-collector outputs not modeled) no testbench

  19. 74x10.sim - Triple 3-Input Positive-NAND Gates
    no testbench

  20. 74x11.sim - Triple 3-Input Positive-AND Gates
    no testbench

  21. 74x113A.sim - Dual J-K Negative-Edge-Triggered Flip-Flops with Preset
    no testbench

  22. 74x114A.sim - Dual J-K Negative-Edge-Triggered Flip-Flops with Preset, Common Clear, and Common Clock
    no testbench

  23. 74x12.sim - Triple 3-Input Positive-NAND Gates (open-collector outputs not modeled) no testbench

  24. 74x13.sim Schmitt Triggers (Hysteresis not yet modeled.)

  25. 74x133.sim - 13-Input Positive-NAND Gates
    no testbench

  26. 74x135.sim - Quadruple EXCLUSIVE-OR Gates
    no testbench

  27. 74x136.sim - Quadruple 2-Input EXCLUSIVE-OR Gates (open-collector outputs not modeled) no testbench

  28. 74x139.sim - Dual 2-Line to 4-Line Decoders/Demultiplexers
    no testbench

  29. 74x14.sim - Schmitt Triggers (Hysteresis not yet modeled.)

  30. 74x15.sim - Triple 3-Input Positive-NAND Gates (open-collector outputs not modeled) no testbench

  31. 74x153.sim - Dual 4-Line to 1-Line Data Selectors/Multiplexers
    testbench - test_74x153.sim (test_74x153.dat)

  32. 74x16.sim - Hex INVERTER BUFFERS (open-collector outputs not modeled) no testbench

  33. 74x17.sim - Hex BUFFERS/DRIVERS (open-collector outputs not modeled) no testbench

  34. 74x19.sim Schmitt Triggers (Hysteresis not yet modeled.)

  35. 74x20.sim - Dual 4-Input Positive-NAND Gates
    no testbench

  36. 74x21.sim - Dual 4-Input Positive-AND Gates
    no testbench

  37. 74x22.sim - Dual 4-Input Positive-NAND Gates (open-collector outputs not modeled) no testbench

  38. 74x24.sim - Schmitt Triggers (Hysteresis not yet modeled.)

  39. 74x25.sim - Dual 4-Input Positive-NOR Gates with Strobe
    no testbench

  40. 74x26.sim - Quadruple 2-Input Positive-NAND Gates
    no testbench

  41. 74x27.sim - Triple 3-Input Positive-NOR Gates
    no testbench

  42. 74x28.sim Quadruple 2-Input Positive-NOR BUFFERS
    no testbench

  43. 74x30.sim - 8-Input Positive-NAND Gates
    no testbench

  44. 74x32.sim - Quadruple 2-Input Positive-OR Gates
    no testbench

  45. 74x33.sim - Quadruple 2-Input Positive-NOR BUFFERS (open-collector outputs not modeled) no testbench

  46. 74x37.sim - Quadruple 2-Input Positive-NAND Gates
    no testbench

  47. 74x38.sim - Quadruple 2-Input Positive-NAND Gates (open-collector outputs not modeled) no testbench

  48. 74x39.sim - Quadruple 2-Input Positive-NAND Gates (open-collector outputs not modeled)

  49. 74x40.sim - Dual 4-Input Positive-NAND Buffers
    no testbench

  50. 74x42.sim - 4-Line BCD to 10-Line Decimal Decoder
    no testbench

  51. 74x51.sim - AND-OR-INVERT Gates
    no testbench

  52. 74x54.sim - 4-Wide AND-OR-INVERT Gates
    no testbench

  53. 74x55.sim - 2-Wide 4-Input AND-OR-INVERT Gates
    no testbench

  54. 74x64.sim - 4-2-3-2 Input AND-OR-INVERT Gates
    no testbench

  55. 74x65.sim - 4-2-3-2 Input AND-OR-INVERT Gates
    no testbench

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