# Digital Logic Models Library

The Digital Logic model library of CSIM contains several simple elements for modeling digital logic circuits. This document describes the models and how to use them. The Digital Logic models are located under \$CSIM_MODEL_LIBS/digilogic. Several example simulations are also included under the examples subdirectory.

Although the models are useful as-is, they are also considered as examples for how to model digital logic elements. The base models can be extended or simplified as needed.

To use these models, include (by-reference) \$CSIM_MODEL_LIBS/digilogic/Library.sim in your top-level diagram.

Digi-Logic models are provided at several abstraction levels.

1. Simple Logic Gates - (And, Or, Nor, Nand, Not, etc..)
2. Modules of Logic Gates - (FlipFlops, Adders, etc..)
3. Standard Parts Models - (74xx Series, USARTS, etc..)
4. Convenience Functions - (Clock, TestBench, Converters, etc..)
5. RTL (Register-Transfer-Level) Blocks - (ALU, Register file, Memory, etc..)
The first three levels operate with binary 0/1 values. (Unknown or hi-Z is represented by -1.) The third level operates on both binary and integer values. The integer values merely represent parallel collections of binary values, but are more efficiently modeled as a single value. The fifth level primarily deals with the integer abstraction, but can easily interface to the binary levels through conversion functions in level 3. The fifth level is not comprised of gate-level models, but represents larger blocks of logic somewhat more abstractly through functional/procedural behavioral descriptions.

1. Gate Models
On the lowest level are the simple on-bit logic gate models:
• Not
• And
• Nand
• Or
• Nor
• Xor
• XNor
The And, Nand, Or, and Nor gates handle any number of inputs (eg, 2, 3, 4, etc..). (Thus there is no need for separate variant models such as Nand_2input, Nand_3input, etc., keeping the library simple. However, a Nand_2in and Nor_3in are provided for curiosity.)

All the simple logic gates have two parameters: Inertial Delay and Propagation Delay. These are defaulted to 0.01 and 0.09, respectively. The defaults may be overridden globally under Edit/Variable in the GUI, and/or on a module or instance basis under the object's properties dialog.

Inertial Delay is the amount of time that an input must be stable before it can affect an eventual output. It basically dampens transients. It is analogous to the similar property of actual logic gates, and is the same as the Inertial-Delay quantity in VHDL. For example, suppose both inputs of an or gate have been zero (low), and a spike of infinitesimal duration raises and lowers one input. Without inertia, the spike would appear on the output after the propagation delay. However due to inertia, the spike will not appear on the output. (You can set this property to zero, if not wanted, but the transient-dampening effect benefits overall simulation speed.)

Propagation Delay is the time-delay for an output to appear after the inertial delay for an input change. In VHDL, this is called the Transfer-Delay.

2. Basic Function Models
Next there are a number of convenient circuit modules built out of the simple logic gates:
• Basic RS-FlipFlop (rsFlipFlop) - Inputs: Clk, R, S. Outputs: Q, NQ.
• Asynchronous RS-FlipFlop with preset and clear (RS_FlipFlop) - Inputs: Clr, Preset, Clk, R, S. Outputs: Q, NQ.
• Master-Slave FlipFlop (msFlipFlop) - Inputs: Clk, R, S. Outputs: Q, NQ.
• D-FlipFlop or Delay-FlipFlop (DFlipFlop) - Inputs: D, Clk. Outputs: Q, NQ.
• T-FlipFlop or Toggle-FlipFlop (TFlipFlop) - Input: T. Output: Q, NQ.
• Half-Adder (HalfAdder) - Inputs: X, Y. Outputs: S, C. (Sum and Carry)

3. Standard Part Models
A library of standard chips has been initiated. See 74xx-Series Logic Family. It contains approximately 64 models presently and will be grown with time. Most have been tested, though not validated for timing against a specific family or speed grade (ie. ttl, nmos, cmos, etc..). However, they can be parameterized to reflect any of these. The test-benches and test-vectors are provided for the non-trivial circuits, as indicated in the referenced document. Validation status is also indicated. (Remember this is a brand new library!)

Example -7442.sim

4. Convenience Models
Next there are a set of convenience models:
• Clock - This model has no inputs and one output. The output is an alternating high/low, or 1/0 pattern. The parameters are: Period, DutyCycle, InitialDelay, and TSTOP. The default values are: 1.0, 0.5, 1e-10, for the first three respectively. TSTOP must be set by the user.

• SplitterJoiner - This is useful for making circuit junctions. Use this to split a signal to send the output of one model to two or more other models. It is usually used to send the value on one link to any number of other output links. (Circuit analogy: Single output-driver to multiple input gates.)

It has one (optional) parameter: InitialValue. This is useful for setting signals to known initial states (eg. 0 or 1). By default, the parameter is set to -1, which means unknown or hi-Z, in which case it does *not* drive any signal initially, but waits until the first valid input arrives.

You could also use this model to join two of more signals, but the circuit analogy is not always clear in this mode. (Circuit analogy: Multiple output-drivers shorted together.) The changes of any input port will be sent to all output ports.

• TestBench - This is a very useful and powerful general purpose object for building test-benches. The test-bench provides two important roles.
A test-bench is a mechanism for:
1. Applying stimulus or test-vectors to your circuit or system.
2. Capturing the responses or output of your circuit or system for viewing, analysis, and/or comparing to expected responses.
The TestBench model has three parameters:
• VectorStimFile - File which provides stimulus or test-vector signals to be applied to your system. The TestBench reads this file. It is a text-file containing lines of the following kinds:
• portname value
• Delay xx
• Mark color
The first case sends the value out the specified output port of the TestBench. The second case, Delay, delays the reading of the VectorStimFile, and subsequent outputs, by the delay quantity. The third case, Mark, places a vertical line on the timeline output (ObservationsFile) of the specified color. This is useful for placing meaningful epic marks, or points-of-reference, into the output, such as when a certain phase of the test began or ended.
• ObservationsFile - Change in the values of any input ports on the TestBench are recorded in this file, along with the time they occurred. When OutputStyle is set to 1, the ObservationsFile is viewable with XGRAPH as a logic-analyzer style time-line plot.
• OutputStyle - Currently there are two options for output style: 0 and 1.
• Style 0 just records the time, value, and portname of any value changes on the input ports to the TestBench. It is a three column output, which may not be directly graphable, by useful for various data collection.
• Style 1 produces a graph-able logic-analyzer style time-line plot. It records both the output of the TestBench, or applied signals, *and* the input signals to the TestBench, or observed responses. The left axis is replaced with the signal names (port-names). The horizontal axis represents time. The applied signals are listed on the bottom, separated by a gray line from the observed response signals on the top of the graph. Binary (0/1) signals are plotted as a high-low oscilloscope-like signal-trace. Integer signals (other than 0/1) are plotted as an envelope containing the value as an annotation within the envelope. This is the default.
• Trace_thickness - Sets the thickness of the trace-lines in the output plot. Default=1.0. If lines are too thin to see easily, a good thicker value is 2.0, or more.
You can hook any number of signal-links to a Testbench. They can have arbitrary names. The port-names are referenced by the VectorStimFile and appear on output in the ObservationsFile.

• Integer2Binary - This is a convenience model. It accepts an input signal containing arbitrary integer values, and converts the integer values to binary values on ports labeled p0 - pN. Where N+1 is the number of binary signal lines. For example, suppose the value 3 arrives on the input port, and there are four output ports labeled, p0, p1, p2, p3. Then the output would be: p3 = 0, p2 = 0, p1 = 1, p0 = 1, being that the integer value 3 is equal to 0011 in 4-bit binary. The least-significant bit is considered p0. The output ports, being binary, can only have the values 0 or 1.

• Binary2Integer - This is a convenience model. It accepts N binary signals, and converts them to an integer, which is sent out the integer output port. The input ports must be labeled p0, p1, ..., with p0 representing the least-significant bit. The input ports, being binary, can only have the values 0 or 1.

## Usage:

As an example, we will follow the process of constructing and testing the Master-Slave FlipFlop module.
1. First, open the GUI:
gui
and import the digilogic library by reference:
File / Import / By Reference
\$CSIM_MODEL_LIBS/digilogic/Library.sim
2. Next, draw the circuit diagram of our design. If you were starting from scratch, you might start by configuring an RS-flipflop module as shown below.
However, in this case the Master-Slave FlopFlip and all constituent pieces are already part of the library. So we only need to draw the top-level diagram, as shown below.
Notice that we instantiated the MS-FlipFlop and added a TestBench. The TestBench was then connected to apply the necessary input signals, and to record the output signals from the MS-FlipFlop, which is the Unit-Under-Test (UUT). By convention, the port-names of the signals connected to the TestBench are given the same names as their connections to the UUT. But you can give them any meaningful names. These are the names that will be used to identify the response signals in the output plots. And these are the names that are used in the VectorStimFile to reference the links to apply signals to. Finally, set the TestBench's VectorStimFile parameter to the file name we will use: test_msff.dat .
3. Now, create the VectorStimFile. We'll call the file:
test_msff.dat
In this file, we will want to set the UUT's input ports to valid values, and then toggle them through a pattern that will test the unit.
Here is an example.:
```	Title = Test of Master Slave FlipFlop
delay 1e-20	! Small initial delay assures all models are ready.
Clk 0		! Zero out the inputs initially.
R 0
S 0
delay 0.2	! Wait a small time.
R 1		! Apply reset and clock pulse.
Clk 1
delay 0.2
R 0		! Lower reset and clock.
Clk 0
delay 0.6
S 1		! Apply Set and clock pulse.
Clk 1
delay 0.2
Clk 0
delay 0.2
S 0
delay 0.8
Clk 1		! Toggle clock to see that values are held.
delay 1
Clk 0
delay 1
R 1
Clk 1
delay 0.5
Clk 0
delay 2
S 1		! Try toggling Set and Reset when clock is low,
delay 1		!  to see what happens.
S 0
delay 2
R 1
delay 1
R 0
Mark Red	! Mark the end of the main test.
delay 1
Clk 1
delay 1		! Let the clock run out ...
Clk 0
S 0
R 0
R 0
delay 1
```
4. Build and Run the simulation.
Tools / Build Simulation
Tools / Run

(Click Run button. Watch simulation to end. Click Exit.)
During the simulation run, you may watch by setting the animation modes of links and boxes to type 1. (Default is no animation, for speed.) You may also wish to flatten portions (or all of) the hierarchy. If you do this for the Master-Slave Flipflop, you might see something like this:
5. Finally, plot the simulation results:
xgraph measured.dat
You will then see:
The bottom-half of the graph shows the applied stimulus signals versus time in green. The upper-half, above the gray dividing-line, shows the response signals from the UUT in violet.